PCB Fabrication and Impedance Control: How to Specify Your Requirements

Technical | June 2026

Introduction: Why Impedance Control Matters

In modern electronics, signals travel across PCB traces at speeds where every millimeter of copper behaves like a transmission line. When impedance is not properly controlled, signals reflect, distort, and radiate — causing data errors, EMI failures, and products that work on the bench but fail in the field. For any design with USB, HDMI, Ethernet, DDR memory, or wireless interfaces, controlled impedance is not optional — it is a fundamental electrical requirement.

Yet many engineers treat impedance control as a manufacturer's problem, simply ticking a box on a fabrication drawing without understanding what they're asking for. This article explains what impedance control really means, how it impacts your design, how to choose the right impedance values for different interfaces, and most importantly — how to communicate your requirements clearly to your PCB manufacturer to get boards that work the first time.

Part 1: How Impedance Affects Your PCB — and Your Product

1.1 What Happens When Impedance Is Wrong

Every PCB trace has a characteristic impedance determined by its geometry (width, thickness, distance to reference plane) and the surrounding dielectric material. When a signal traveling along a trace encounters an impedance change — at a via, a connector, or simply because the trace width changes — part of the signal energy reflects back toward the source. These reflections cause:

• Signal distortion: Reflected energy superimposes on the original signal, degrading the eye diagram and increasing bit error rates. A USB 3.0 link that should run at 5 Gbps may fail to enumerate or drop packets at much lower speeds
• Timing errors: In clock and data signals, reflections shift the apparent edge timing, reducing setup and hold margins. DDR memory interfaces are particularly sensitive — a few picoseconds of added jitter can cause memory corruption
• Increased EMI: Reflected energy doesn't just stay on the trace — it radiates. A board that passes functional testing can still fail FCC or CE emissions testing because impedance mismatches create unintended antennas
• Reduced noise margin: Even if the link "works," marginal impedance means the receiver is operating closer to its decision threshold, making the product more susceptible to field failures due to temperature, aging, or environmental noise

1.2 When Does Impedance Control Become Necessary?

A useful rule of thumb: when the trace length exceeds approximately 1/6 of the signal's rise-time-equivalent wavelength, the trace behaves as a transmission line and impedance must be controlled. For a typical 1 ns rise time on FR-4 (dielectric constant Dk ≈ 4.0), this critical length is approximately 25–30 mm. In practice, this means:

• Always control impedance for USB, HDMI, Ethernet, PCIe, SATA, MIPI, LVDS, DDR memory, and RF antenna feeds
• Strongly consider impedance control for SPI, I2C, and UART when traces exceed 100 mm or run at clock speeds above 10 MHz
• Generally not required for slow GPIO, LED drivers, relay controls, or traces shorter than 25 mm with rise times above 5 ns

1.3 The Cost of Getting It Wrong

Fixing an impedance problem after PCB fabrication is expensive. A controlled-impedance board that misses its target typically requires a full re-spin: new stack-up design, new layout adjustments, new prototype fabrication, and re-testing. Depending on layer count and complexity, each re-spin costs $2,000–$10,000 and adds 3–6 weeks to the project timeline. If the problem is only discovered during compliance testing (EMC, signal integrity validation), the cost multiplies — including re-testing fees, delayed product launch, and potentially lost market opportunities.

Part 2: Choosing the Right Impedance Values

2.1 Standard Impedance Values by Interface

Most high-speed interfaces have well-established impedance standards. These are not arbitrary — they are defined by industry consortia (USB-IF, HDMI Forum, PCI-SIG) to ensure interoperability between devices from different manufacturers. Always use the standard value for the interface you're designing.

2.2 Single-Ended vs. Differential Impedance — Understanding the Difference

This distinction causes more confusion in fabrication notes than almost any other PCB specification:

• Single-ended impedance (Z0): The impedance of a single trace referenced to the ground/power plane. Measured by driving the trace and measuring the return current through the reference plane. Used for RF traces, DDR address/command lines, and general high-speed signals
• Differential impedance (Zdiff): The impedance between two traces driven with equal and opposite signals. Measured between the two traces of a differential pair. Used for USB, HDMI, Ethernet, PCIe, LVDS, and MIPI

These two values are related but not interchangeable. A pair of 50Ω single-ended traces, when routed as a differential pair with tight coupling, typically produces a differential impedance of approximately 100Ω — which is why 100Ω differential is so common. When filling out your fabrication notes, specify Zdiff for differential pairs and Z0 for single-ended traces — don't mix them up.

2.3 Tolerance Selection — ±10% or ±5%?

PCB manufacturers typically offer two impedance tolerance classes:

• ±10% (Standard): Achievable by most manufacturers on standard FR-4 materials. Sufficient for most applications including USB 2.0, HDMI, Ethernet, and general high-speed digital. This is the default and costs no premium
• ±5% (Tight): Requires tighter process control, often involves selecting specific dielectric materials with more consistent Dk values, and may require additional test coupons. Adds approximately 10–25% to the PCB fabrication cost. Recommended for USB 3.0/3.1, PCIe Gen 3+, DDR4, and long backplane traces where margin is limited

Part 3: How to Specify Impedance Requirements to Your Manufacturer

3.1 What the Manufacturer Needs From You

A clear impedance specification includes all of the following. Missing any element forces the manufacturer to make assumptions — and assumptions lead to boards that don't meet your expectations.

• Which nets require controlled impedance: Use net classes in your CAD tool (e.g., "USB_DIFF_90", "ETH_DIFF_100", "RF_50") and list them explicitly in the fabrication notes. Don't just say "controlled impedance" — say which nets, on which layers, at what value, single-ended or differential, and at what tolerance
• The target impedance value and type: For each net class, state the value (e.g., 90Ω), the type (differential or single-ended), and the tolerance (e.g., ±10%)
• Which layers contain controlled-impedance traces: Impedance is layer-specific. A 0.15 mm-wide trace on Layer 1 (microstrip) may produce 50Ω while the same width on Layer 3 (stripline) produces a different impedance. The manufacturer needs to know which layers to control
• Your proposed stack-up (if you have one): If you've already designed the board with a specific stack-up in mind, provide it. The manufacturer will verify whether your trace dimensions achieve the target impedance on that stack-up and suggest adjustments if needed
• Reference plane assignment: For each controlled-impedance layer, specify which adjacent layer serves as the reference plane (usually the nearest ground or power plane)

3.2 Example: A Well-Specified Impedance Requirement

Here is an example of how to write impedance requirements clearly in your fabrication notes. Compare this to the vague "controlled impedance required" that many designs submit:

3.3 The Impedance Test Coupon — Your Proof of Performance

An impedance test coupon (also called an impedance coupon or TDR coupon) is a small test structure placed on the same production panel as your PCB. It contains traces with the same width, spacing, and layer stack-up as the controlled-impedance traces on your board. The manufacturer uses Time Domain Reflectometry (TDR) to measure the impedance of the coupon traces and provides a test report showing the measured values.

Key points about test coupons:

• Always request them. A test coupon is the only way to verify that the manufacturer actually achieved your target impedance. Without it, you're trusting that the process was correct — and you won't know there's a problem until your board fails in testing
• Specify which net classes need coupons. If you have three different impedance targets (e.g., 50Ω single-ended, 90Ω differential, 100Ω differential), request a coupon for each
• Review the TDR report before assembly. If measured impedance is out of tolerance, reject the bare boards before components are placed. It's far cheaper to re-fabricate bare boards than to scrap assembled PCBs
• Standard tolerance for TDR measurement: Most manufacturers guarantee impedance within ±10% of the target value on test coupons. If you need tighter verification, discuss it with the manufacturer before placing the order

Part 4: Common Impedance Pitfalls and How to Avoid Them

4.1 The Soldermask Effect

Soldermask has a dielectric constant (Dk ≈ 3.5–4.0) that differs from air (Dk = 1.0). On microstrip traces (outer layers), the soldermask coating increases the effective dielectric constant around the trace, which reduces the characteristic impedance by approximately 2–4Ω compared to an uncoated trace of the same dimensions. If your field solver or CAD tool calculates impedance without accounting for soldermask, your actual fabricated impedance will be lower than simulated. Always enable the soldermask model in your impedance calculator, and specify the soldermask type (LPI, dry film) and thickness in your stack-up documentation.

4.2 Reference Plane Discontinuities

A controlled-impedance trace requires a continuous, uninterrupted reference plane for its entire length. When a trace crosses a gap, slot, or split in the reference plane — such as a clearance hole around a via field, or a split between power and ground planes — the impedance changes abruptly at the discontinuity. The return current must detour around the gap, creating a large loop area and a significant impedance spike. Rule: Never route controlled-impedance traces across a reference plane split. If splits are unavoidable for power distribution, route sensitive signals only over the continuous ground region, well away from split boundaries.

4.3 Via Discontinuities

Every via introduces an impedance discontinuity. The via barrel has different geometry than the trace, and the transition between layers changes the reference plane. For high-speed signals above 1 Gbps (USB 3.0, PCIe, HDMI 2.0), via design becomes critical: minimize the number of vias on each controlled-impedance net, use back-drilling to remove unused via stubs that cause reflections, and consider adding ground return vias adjacent to signal vias to maintain a continuous return path through the layer transition.

4.4 Laminate Material Variations

Standard FR-4 is not a precision dielectric material. Its Dk can vary ±10% from batch to batch, and it changes with frequency and temperature. For designs with tight impedance margins or very long traces (backplanes, large server boards), consider specifying a low-Dk-tolerance laminate such as Isola FR408HR, Nelco N4000-13, or Rogers 4350B for RF sections. These materials have more tightly controlled Dk values and lower loss tangents, resulting in more consistent impedance across production batches.

Conclusion

Controlled impedance is a design requirement, not a manufacturing afterthought. Getting it right means understanding which interfaces need impedance control, choosing the correct values and tolerances, and communicating your requirements to the PCB manufacturer with precision and clarity. The difference between a vague "controlled impedance required" note and a well-specified impedance table with net classes, layers, and test coupon requests is the difference between a board that works the first time and a board that triggers an expensive, time-consuming re-spin.

At FANYE Technology, we handle impedance-controlled PCB design daily — from 90Ω USB differential pairs on 4-layer IoT sensors to tightly-toleranced 85Ω PCIe lanes on 8-layer industrial controllers. Our design team works directly with PCB manufacturers to validate stack-ups, specify impedance requirements, and review TDR test reports, ensuring that your boards meet their electrical targets before a single component is placed. Whether you need a complete turnkey design or a DFM review of your existing layout, we're ready to help.